1. Field of the Invention
The present invention relates to an integrated circuit having dynamic memory cells.
2. Description of the Prior Art
Dynamic memory cells store a logical "1" or "0" as a high or low voltage level on a capacitor that is accessed by an access transistor. Early generation dynamic memories used a three-transistor cell, but the one-transistor cell is presently considered optimum for purposes of reducing the area required to implement the memory cell on an integrated circuit. Dynamic memories typically utilize refresh circuitry external to the memory cells for periodically restoring the full high or low voltage level in each cell, which may otherwise be lost due to current leakage from the storage capacitor. The use of "self-refreshed" memory cells, which eliminate the need for a separate refresh operation, has also been investigated. Both three-transistor and two-transistor self-refreshed cells have been proposed. For example, U.S. Pat. No. 4,070,653 describes a two-transistor self-refreshed cell, wherein a switchable resistor is switched between a high and low impedance state, depending on whether a logic "1" or "0" is stored. However, the extra space required for the self-refreshing circuitry makes the one-transistor cell the presently preferred choice in commercial practice. With memory densities of one megabit (1M bit) currently in production, and densities of 4M bit and 16M bit under development, the need to conserve the space required for each cell becomes even more important.
The lower limit to the cell size is dictated in part by the size of the capacitor, which must store sufficient electrical charge to allow the information to be reliably read out when required. Current efforts for increasing the density of memory cells are largely directed toward decreasing the area required for the capacitor, without substantially decreasing its capacitance. These efforts include the use of a thinner dielectric layer to separate the capacitor plates, and the use of materials having a higher dielectric constant than those previously used. The use of a vertical capacitor plate (the so-called "trench capacitor") is another technique for saving integrated circuit area. It is also known to locate the capacitor so as to overlie the access transistor, in the so-called "stacked capacitor" cell arrangement.
However, each of these approaches has fabrication difficulties that make it desirable to find improved memory cell designs that conserve integrated circuit area.